05903495 is referenced by 435 patents and cites 4 patents.

A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data items read from said memory cells, wherein data items read from said memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from said memory cells are held in the remaining (m-k) latch circuits, during data-reading operation.

Title
Semiconductor device and memory system
Application Number
8/819484
Publication Number
5903495
Application Date
March 17, 1997
Publication Date
May 11, 1999
Inventor
Tomoharu Tanaka
Yokohama
JP
Ken Takeuchi
Tokyo
JP
Agent
Banner & Witcoff
Assignee
Kabushiki Kaisha Toshiba
JP
IPC
G11C
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