05901093 is referenced by 4 patents and cites 20 patents.

An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates an address masking function into the redundant bit decoder during block write operations and also bypasses a masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines. It eliminates the need for replacing all the selected bit lines and, thereby, saves silicon area and maximizes the utilization of available redundant bit elements.

Title
Redundancy architecture and method for block write access cycles permitting defective memory line replacement
Application Number
703077
Publication Number
5901093
Application Date
June 5, 1995
Publication Date
May 4, 1999
Inventor
Thomas Walter Wyckoff
Jeffersonville
VT, US
Steven William Tomashot
Jericho
VT, US
Robert Tamlyn
Jericho
VT, US
Nathan Rafael Hiltebeitel
Essex Jct.
VT, US
Agent
Robert A Walsh
Mark F Chadurjian
Assignee
International Business Machines Corporation
NY, US
IPC
G11C 7/00
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