05890217 is referenced by 61 patents and cites 22 patents.

A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Title
Coherence apparatus for cache of multiprocessor
Application Number
8/598243
Publication Number
5890217
Application Date
February 7, 1996
Publication Date
March 30, 1999
Inventor
Toshiyuki Shimizu
Kawasaki
JP
Takeshi Horie
Kawasaki
JP
Hiroaki Ishihata
Kawasaki
JP
Jun Sakurai
Sendai
JP
Yozo Nakayama
Aza Unoke-machi
JP
Satoshi Shinohara
Kawasaki
JP
Takatsugu Sasaki
Kawasaki
JP
Junji Nishioka
Kawasaki
JP
Hirohide Sugahara
Kawasaki
JP
Takayuki Shimamura
Kawasaki
JP
Toshiyuki Muta
Kawasaki
JP
Naohiro Shibata
Kawasaki
JP
Akira Kabemoto
Kawasaki
JP
Agent
Staas & Halsey
Assignee
PFU
JP
Fujitsu
JP
IPC
G06F 13/00
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