05889436 is referenced by 70 patents and cites 37 patents.

A phase-locked loop (PLL) frequency synthesizer is described which incorporates a fractional pulse swallowing circuit. The fractional pulse swallowing circuit does not add or delete pulses but extends or shortens pulses by a fractional amount. This avoids large phase errors generated by a phase detector in the PLL. In the preferred embodiment, the PLL uses a voltage controlled oscillator (VCO) formed of a ring oscillator. The outputs of the stages of the ring oscillator are applied to input terminals of a multiplexer. The multiplexer is controlled at certain times to output a different tapped signal from the ring oscillator to effectively adjust the phase of the signal output from the multiplexer. By so controlling the multiplexer, fractional pulses are subtracted or added at intervals to either increase or decrease the average frequency of the signal output from the multiplexer. The output of the VCO is fed back to the input of a phase detector along with a reference frequency. Alternatively, the output of the pulse swallower, and not the VCO, provides the feedback signal for the phase detector.

Title
Phase locked loop fractional pulse swallowing frequency synthesizer
Application Number
8/742331
Publication Number
5889436
Application Date
November 1, 1996
Publication Date
March 30, 1999
Inventor
Laurence D Lewicki
Sunnyvale
CA, US
Kern Wai Wong
Sunnyvale
CA, US
Pak Ho Yeung
San Jose
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Agent
Brian D Ogonowsky
Assignee
National Semiconductor Corporation
CA, US
IPC
H03L 7/099
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