05888884 is referenced by 148 patents and cites 23 patents.

Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.

Title
Electronic device pad relocation, precision placement, and packaging in arrays
Application Number
23140
Publication Number
5888884
Application Date
January 2, 1998
Publication Date
March 30, 1999
Inventor
Robert John Wojnarowski
Ballston Lake
NY, US
Agent
Marvin Snyder
Ann M Agosti
Assignee
General Electric Company
NY, US
IPC
H01L 21/301
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