05880981 is referenced by 67 patents and cites 7 patents.

The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.

Title
Method and apparatus for reducing the power consumption in a programmable digital signal processor
Application Number
8/695617
Publication Number
5880981
Application Date
August 12, 1996
Publication Date
March 9, 1999
Inventor
Avadhani Shridhar
Sunnyvale
CA, US
Hirotsugu Kojima
Foster City
CA, US
Agent
Flehr Hohbach Test Albritton & Herbert
Assignee
Hitachi America
NY, US
IPC
G06F 7/52
G06F 7/38
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