05872902 is referenced by 109 patents and cites 49 patents.

A system for rendering visual images that combines sophisticated anti-aliasing and pixel blending techniques with control pipelining in hardware embodiment. A highly-parallel rendering pipeline performs sophisticated polygon edge interpolation, pixel blending and anti-aliasing rendering operations in hardware. Primitive polygons are transformed to subpixel coordinates and then sliced and diced to create "pixlink" elements mapped to each pixel. An oversized frame buffer memory allows the storage of many pixlinks for each pixel. Z-sorting is avoided through the use of a linked-list data object for each pixlink vector in a pixel stack. Because all image data values for X, Y, Z, R, G, B and pixel coverage A are maintained in the pixlink data object, sophisticated blending operations are possible for anti-aliasing and transparency. Data parallelism in the rendering pipeline overcomes the processor efficiency problem arising from the computation-intensive rendering algorithms used in the system of this invention. Single state machine control is made possible through linked data/control pipelining.

Title
Method and apparatus for rendering of fractional pixel lists for anti-aliasing and transparency
Application Number
69180
Publication Number
5872902
Application Date
June 19, 1995
Publication Date
February 16, 1999
Inventor
Curt Stehley
Solana Beach
CA, US
James V Henson
Poway
CA, US
Manuel Rey Enriquez
Oceanside
CA, US
John Rigg
Poway
CA, US
Roman Kuchkuda
San Diego
CA, US
Agent
Nydegger & Associates
Assignee
Nihon Unisys
JP
IPC
G06T 11/40
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