05870350 is referenced by 195 patents and cites 11 patents.

A high performance, high bandwidth memory bus architecture and module. The module may be a card that includes standard synchronous DRAM (SDRAM) chips and reduces latency and pin count. Four bus pins separate input commands from data and establish parallel system operations. By maintaining "packet" type transactions, independent memory operations can be enhanced from that of normal SDRAM operations. The architecture divides its buses into command and data inputs that are separate from output data.

Title
High performance, high bandwidth memory bus architecture utilizing SDRAMs
Application Number
8/861101
Publication Number
5870350
Application Date
May 21, 1997
Publication Date
February 9, 1999
Inventor
Erik L Hedberg
Essex Junction
VT, US
Claude L Bertin
South Burlington
VT, US
Agent
Whitham Curtis & Whitham
Agent
Robert A Walsh
Assignee
International Business Machines Corporation
NY, US
IPC
G11C 8/00
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