05852525 is referenced by 1 patents and cites 4 patents.

An automatic clock signal phase adjusting circuit for use with a digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method. The automatic clock signal phase adjusting circuit comprises: a pattern detection circuit for detecting at least one of patterns "1, 0, -1" and "-1, 0, 1" from a reproduced signal; a level detection circuit for detecting the levels of the reproduced signal in effect when the pattern detection circuit detects 0's; a clock reproduction circuit for reproducing a clock signal from the reproduced signal; and a phase adjustment circuit for adjusting the phase of the clock signal reproduced by the clock reproduction circuit based on the output signal from the level detection circuit.

Title
Automatic clock signal phase adjustment in which a pattern including 0s is detected and integrated to effect the phase adjustment
Application Number
107074
Publication Number
5852525
Application Date
February 14, 1997
Publication Date
December 22, 1998
Inventor
Haruyuki Yoshioka
Tokyo
JP
Takahito Seki
Kanagawa
JP
Agent
Frommer Lawrence & Haug
Agent
William S Frommer
Assignee
Sony Corporation
JP
IPC
G11B 5/09
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