05843799 is referenced by 102 patents and cites 122 patents.

A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

Title
Circuit module redundancy architecture process
Application Number
787984
Publication Number
5843799
Application Date
January 13, 1997
Publication Date
December 1, 1998
Inventor
Wingyu Leung
Cupertino
CA, US
Fu Chieh Hsu
Saratoga
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Assignee
Monolithic System Technology
CA, US
IPC
H01L 21/00
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