05838177 is referenced by 159 patents and cites 75 patents.

An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.

Title
Adjustable output driver circuit having parallel pull-up and pull-down elements
Application Number
8/779344
Publication Number
5838177
Application Date
January 6, 1997
Publication Date
November 17, 1998
Inventor
Brent Keeth
Boise
ID, US
Agent
Schwegman Lundberg Woessner & Kluth P A
Assignee
Micron Technology
ID, US
IPC
H03K 3/00
View Original Source