05835697 is referenced by 23 patents and cites 13 patents.

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

Title
Information processing system
Application Number
8/674786
Publication Number
5835697
Application Date
July 3, 1996
Publication Date
November 10, 1998
Inventor
Takato Noda
Sendai
JP
Shinya Katoh
Kawasaki
JP
Takumi Takeno
Kawasaki
JP
Kazuhiro Nonomura
Kawasaki
JP
Koichi Odahara
Kawasaki
JP
Yoshio Hirose
Kawasaki
JP
Takumi Kishino
Kawasaki
JP
Yasutomo Sakurai
Kawasaki
JP
Toru Watabe
Kawasaki
JP
Agent
Staas & Halsey
Assignee
Fujitsu
JP
IPC
G06F 11/00
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