05832304 is referenced by 32 patents and cites 16 patents.

An improved memory request storage and allocation system using parallel queues to retain different categories of memory requests until they can be acted on by the main memory. Memory requests in the parallel queues are allowed to access the main memory according to a queue priority scheme. The queue priority scheme is based on an adjustable ratio, which determines the rate at which memory requests from one queue are allowed to access the main memory versus memory requests from other queues. Registers for bypassing the adjustable ratio eliminate delays by prohibiting the queue priority circuitry from attempting to retrieve a non-existent memory request from a queue. Conflict detection circuitry maintains proper instruction order in the parallel queue architecture by ensuring that subsequent memory requests, which have the same address as a memory request already in the queue, are placed in the same queue in the order that they were entered into the queue.

Title
Memory queue with adjustable priority and conflict detection
Application Number
8/404791
Publication Number
5832304
Application Date
March 15, 1995
Publication Date
November 3, 1998
Inventor
Roger L Gilbertson
Minneapolis
MN, US
Jerome G Carlin
Shoreview
MN, US
Mitchell A Bauman
Circle Pines
MN, US
Agent
Mark T Starr
Charles A Johnson
Assignee
Unisys Corporation
PA, US
IPC
G06F 13/18
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