05831836 is referenced by 91 patents and cites 29 patents.

An integrated circuit device package of this invention includes a flexible substrate having an upper patterned insulative layer, and a lower patterned conductive layer including a plurality of package leads. An integrated circuit die is fixed within a void of the upper surface of the flexible substrate. Electrical connections between the integrated circuit die and the package leads are provided. A rigid upper protective layer is present. The rigid upper protective layer encloses the integrated circuit die, and at least partially covers the top surface of the upper insulative layer. The semiconductor device package further comprises a rigid or semi-rigid metal lower protective layer opposite the upper protective layer including a ground plane proximal to the electrical leads and a power plane distal to the leads. Methods of production are also given.

Title
Power plane for semiconductor device
Application Number
7/828468
Publication Number
5831836
Application Date
January 30, 1992
Publication Date
November 3, 1998
Inventor
John McCormick
Redwood City
CA, US
Jon Long
Livermore
CA, US
Agent
Karen S Perkins
Assignee
LSI Logic
CA, US
IPC
H05K 7/02
H05K 1/00
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