05815462 is referenced by 99 patents and cites 4 patents.

A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

Title
Synchronous semiconductor memory device and synchronous memory module
Application Number
8/800905
Publication Number
5815462
Application Date
February 12, 1997
Publication Date
September 29, 1998
Inventor
Seiji Sawada
Hyogo
JP
Yasumitsu Murai
Hyogo
JP
Takashi Araki
Hyogo
JP
Hisashi Iwamoto
Hyogo
JP
Yasuhiro Konishi
Hyogo
JP
Agent
McDermott Will & Emery
Assignee
Mitsubishi Electric Engineering
JP
Mitsubishi Denki Kabushiki Kaisha
JP
IPC
G11C 8/00
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