05812803 is referenced by 15 patents and cites 2 patents.

A method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller includes a memory controller having a data controller unit and a data path unit. Signals are passed between the data controller unit and the data path unit, thereby providing an interface between the two units. The data controller receives control signals from the bus and provides commands to the data path unit in response to these control signals. The commands provided to the data path unit enable the data path unit to transfer data to and from the bus and memory device.

Title
Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller
Application Number
8/536662
Publication Number
5812803
Application Date
September 29, 1995
Publication Date
September 22, 1998
Inventor
Patrick F Stolt
Beaverton
OR, US
Stephen S Pawlowski
Beaverton
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 12/00
G06F 13/38
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