05809281 is referenced by 75 patents and cites 13 patents.

A field programmable gate array (FPGA) includes a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM. In accordance with the present invention, each configurable function block includes a volatile logic array comprised of an array of "AND" gates and an array of "OR" gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are then capable of serving the user of the FPGA in two modes of operation. In a first mode of operation, logic mode, the SRAM cells provide for the programmable connections which direct the logic operations in the volatile logic array. In a second mode of operation, memory mode, the SRAM cells function as a block of SRAM which can then be written to, and read from, using standard SRAM access signals.

Title
Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM
Application Number
39972
Publication Number
5809281
Application Date
January 28, 1997
Publication Date
September 15, 1998
Inventor
Duane H Chinnow Jr
Folsom
CA, US
Randy Charles Steele
Folsom
CA, US
Agent
Townsend and Townsend and Crew
Assignee
Altera Corporation
CA, US
IPC
G06F 12/00
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