05802395 is referenced by 132 patents and cites 24 patents.

Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. There are two parts to the solution of reducing data line capacitance to an acceptable system limit. The first part involves designing a memory module with in-line bus switches. The bus switches are placed between the module tabs (system) and random access memory devices and are either in a high impedance (off) or active state. When in the high impedance state, the effective loading of the module is that of the bit switch device. The second part of the solution is to embed logic into an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches. The bus switches become active on the falling edge of the system's RAS select line and stay active until the latter of the system's RAS or column address strobe (CAS) select lines going inactive, thereby supporting both Fast Page Mode (FPM) and Extended Data Output (EDO) operation. The circuit performs this task by decoding the system's RAS and CAS select lines and driving a signal to enable the bus switches.

Title
High density memory modules with improved data bus performance
Application Number
8/676609
Publication Number
5802395
Application Date
July 8, 1996
Publication Date
September 1, 1998
Inventor
Bruce G Hazelzet
Essex Junction
VT, US
Mark W Kellogg
Essex Junction
VT, US
Brian J Connolly
Williston
VT, US
Agent
Whitham Curtis & Whitham
Agent
Robert A Walsh
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 13/38
G06F 13/10
G06F 12/06
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