05796667 is referenced by 15 patents and cites 25 patents.

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Title
Bit map addressing schemes for flash memory
Application Number
253902
Publication Number
5796667
Application Date
April 19, 1996
Publication Date
August 18, 1998
Inventor
Mark E Bauer
Cameron Park
CA, US
Sherif Sweha
El Dorado Hills
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G11C 7/00
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