05787255 is referenced by 88 patents and cites 5 patents.

A special memory overlay circuit uses a first DRAM buffer memory in combination with a second faster SRAM buffer memory to reduce the time required to translate information into different network protocols. Packet data is stored in the DRAM buffer memory and packet headers requiring manipulation are stored in the SRAM buffer memory. Because the SRAM has a faster data access time than the DRAM buffer memory, a processor can reformat the packet header into different network protocols in a shorter amount of time. Packet headers also use a relatively small amount of memory compared to remaining packet data. Since the SRAM buffer memory is only used for storing packet headers, relatively little additional cost is required to utilize the faster SRAM memory while substantially increasing network performance.

Title
Internetworking device with enhanced protocol translation circuit
Application Number
8/631790
Publication Number
5787255
Application Date
April 12, 1996
Publication Date
July 28, 1998
Inventor
Shashi Kumar
Fremont
CA, US
Jonathan M Parlan
San Jose
CA, US
Agent
Marger Johnson et al
Assignee
Cisco Systems
CA, US
IPC
G06F 12/00
View Original Source