05771361 is referenced by 3 patents and cites 8 patents.

In a data processor, an internal memory stores instruction codes and a central processing unit reads an instruction code form the memory and produces an external access request if it contains an instruction to access an external memory which is connected to an external terminal. A bus controller is responsive to the request for producing a data timing signal and one of read and write signals. An external address bus and an external data bus are connected to the bus controller. An internal address bus is connected to the CPU for transporting an internal address signal. A selecting circuit is responsive to a first mode switching signal for coupling one of the external address bus and the external data bus to the external terminal and determining the direction of the data signal transported by the external data bus when it is coupled to the external terminal in accordance with the data timing signal and one of the read and write signals, and responsive to a second mode switching signal for coupling the internal address bus to the external terminal in the absence of the data timing signal and the read and write signals. For an external memory having separate data and address terminals, a second external terminal is additionally provided for coupling the external address bus direct to the address terminal of the external memory through the second external terminal, instead of through the selecting circuit.

Data processor having shared terminal for monitoring internal and external memory events
Application Number
Publication Number
Application Date
June 14, 1995
Publication Date
June 23, 1998
Hiroshi Katsuta
Yusuke Tokieda
Foley & Lardner
NEC Corporation
G06F 13/00
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