05768106 is referenced by 8 patents and cites 5 patents.

A layered circuit-board designing method and layered circuit-board where circuit-boards to be overlaid are connected at the center or an arbitrary position of each circuit-board. The layered circuit-board includes an upper-layer first circuit-board, a lower-layer third circuit-board, and an intermediate-layer second circuit-board between the first and third circuit-boards. A first connector is mounted on the first circuit-board, a second connector is mounted on the third circuit-board, a third connector is mounted on the top surface of the second circuit-board, while maintaining the positional relation between the third connector and the first connector, and a fourth connector is mounted on the bottom surface of the second circuit-board, while maintaining the positional relation between the fourth connector and the second connector. In addition, through holes are provided at pins of the third and fourth connectors for passing through the front and bottom surfaces of the second circuit-board.

Title
Layered circuit-board designing method and layered circuit-board
Application Number
8/661473
Publication Number
5768106
Application Date
June 11, 1996
Publication Date
June 16, 1998
Inventor
Akira Ichimura
Kawasaki
JP
Agent
Fitpatrick Cella Harper & Scinto
Assignee
Canon Kabushiki Kaisha
JP
IPC
H05K 1/14
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