05767549 is referenced by 202 patents and cites 9 patents.

An integrated circuit is described incorporating a substrate, a layer of insulator, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between mesas, electronic devices on the mesas, and interconnection wiring. The invention overcomes the problem of a floating gate due to charge accumulation below the channel of MOS FET's.

Title
SOI CMOS structure
Application Number
8/678442
Publication Number
5767549
Application Date
July 3, 1996
Publication Date
June 16, 1998
Inventor
Yuan Taur
Bedford
NY, US
Devendra Kumar Sadana
Pleasantville
NY, US
Wei Chen
Croton-on-Hudson
NY, US
Agent
Robert M Trepp
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 27/01
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