05764954 is referenced by 129 patents and cites 17 patents.

In a Field Programmable Gate Array ("FPGA") design system, a configuration is generated. A path of the configuration is selected as a critical path for optimization. The critical path is optimized by rerouting connections between the logical primitives of the critical path. Prior to the rerouting, the logical primitives of the critical path may be optimally placed within the FPGA configuration. Optimal performance of the critical path is thus achieved.

Title
Method and system for optimizing a critical path in a field programmable gate array configuration
Application Number
8/518515
Publication Number
5764954
Application Date
August 23, 1995
Publication Date
June 9, 1998
Inventor
Eric Ernest Millham
St. George
VT, US
Steven Paul Hartman
Jericho
VT, US
Christine Marie Fuller
Williston
VT, US
Agent
Heslin & Rothenberg P C
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 9/455
View Original Source