05764946 is referenced by 74 patents and cites 29 patents.

A superscalar microprocessor is provided employing a way prediction unit which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being read from the instruction cache. The microprocessor may achieve high frequency operation while using an associative instruction cache. An instruction fetch can be made every clock cycle using the predicted fetch address from the way prediction unit until an incorrect next fetch address or an incorrect way is predicted. The instructions from the predicted way are provided to the instruction processing pipelines of the superscalar microprocessor each clock cycle.

Title
Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
Application Number
420641
Publication Number
5764946
Application Date
April 8, 1997
Publication Date
June 9, 1998
Inventor
James K Pickett
Austin
TX, US
Thang M Tran
Austin
TX, US
Agent
Conley Rose & Tayon
Agent
B Noel Kivlin
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 13/00
G06F 12/00
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