05754819 is referenced by 23 patents and cites 5 patents.

A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by processing the raw address information faster than the addition used in the prior art. XOR memory addressing replaces the addition of the base and offset address components with an XOR operation, eliminating carry propagation and reducing overall latency. In another embodiment, a sum-addressed memory (SAM) also eliminates the carry propagation and thus reduce the latency while providing the correct base+offset index to access the memory word line corresponding to the correct addition; thus a SAM causes no XOR duplicate problems.

Title
Low-latency memory indexing method and structure
Application Number
8/282525
Publication Number
5754819
Application Date
July 28, 1994
Publication Date
May 19, 1998
Inventor
Gary R Lauterbach
Los Altos
CA, US
William L Lynch
Palo Alto
CA, US
Agent
Steven F Flehr Hohbach Test Albritton and Herbert Caserza
Assignee
Sun Microsystems
CA, US
IPC
G06F 12/08
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