05752035 is referenced by 183 patents and cites 3 patents.

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a set of program instructions, to provide an on chip reprogrammable instruction set accelerator RISA. Reprogrammable execution units may be made using field programmable gate array technology having configuration stores. Techniques for translating a computer program into executable code relying on the RISA involve providing a library of defined and programmed instructions, and compiling a program using the library to produce an executable version of the program using both defined and programmed instructions. The executable version can be optimized to conserve configuration resources for the programmable execution unit, or to optimize speed of execution. Thus, seldom used programmed instructions in the final object code can be replaced with segments of defined instructions to conserve configuration resources. Alternatively, specially prepared sets of programmed instructions can be used to compile programs. A variety of versions are formed using separate sets of programmed instructions and the best final version is selected. In addition, commonly used segments of instructions can be synthesized into a programmed instruction dynamically.

Title
Method for compiling and executing programs for reprogrammable instruction set accelerator
Application Number
417337
Publication Number
5752035
Application Date
June 7, 1995
Publication Date
May 12, 1998
Inventor
Stephen M Trimberger
San Jose
CA, US
Agent
Haynes & Davis Crosby Heafy Roach & May
Agent
Jeanette S Harms
Assignee
Xilinx
CA, US
IPC
G06F 15/76
G06F 9/44
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