05748560 is referenced by 40 patents and cites 3 patents.

An internal read/write termination detect circuit generates a one shot pulse signal when a read operation activation signal and a write operation activation signal are both set to an inactive state. An internal operation activation signal generation circuit holds an auto precharge enable signal by a flipflop according to an auto precharge command to generate a precharge operation trigger signal according to the auto precharge enable signal and the one shot pulse signal. An internal operation activation signal is reset to an inactive state. The auto precharge command is made valid to carry out an internal precharge operation only when internal write/read operation is completed. A synchronous semiconductor memory device with easy control of an auto precharge command and reduced in layout area is provided.

Title
Synchronous semiconductor memory device with auto precharge operation easily controlled
Application Number
8/740175
Publication Number
5748560
Application Date
October 28, 1996
Publication Date
May 5, 1998
Inventor
Seiji Sawada
Hyogo
JP
Agent
McDermott Will & Emery
Assignee
Mitsubishi Denki Kabushiki Kaisha
JP
IPC
G11C 7/00
G11C 8/00
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