05748559 is referenced by 9 patents and cites 3 patents.

The present invention provides a circuit for programming a logic device comprising a first register for shifting data to a memory array, a second register for decoding an address space for a particular word within the logic device. The memory array has an address input and a data input coupled to the first and second registers. One of the registers is implemented as a registered counter block while the other register can be implemented as either a shift register, for a low pin count design, and/or a parallel load register for a higher pin counter and higher performance design.

Title
Circuit for high speed serial programming of programmable logic devices
Application Number
8/587659
Publication Number
5748559
Application Date
January 17, 1996
Publication Date
May 5, 1998
Inventor
James B MacArthur
Santa Clara
CA, US
S Babar Raza
Sunnyvale
CA, US
Agent
Bliss McGlynn P C
Assignee
Cypress Semiconductor Corporation
CA, US
IPC
G11C 8/00
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