05748516 is referenced by 52 patents and cites 27 patents.

Logic for selectively forcing arithmetic results allows a floating point unit to bypass the normal flow through arithmetic units and pipelines depending on the particular floating point operation and operand conditions. Certain forced results (e.g., forced zeros, infinities, and those corresponding to certain invalid operand conditions) may bypass arithmetic units or pipelines and rounding circuitry entirely. On the other hand, other operand dependent results (e.g., the result of X+0 and results of operations involving a NaN operand or operands) may only partially bypass the normal flow. By providing logic for selectively forcing results, arithmetic pipelines may be freed for subsequent instructions in the instruction stream. Logic for selectively forcing arithmetic results may be particularly attractive in a superscalar processor. In a superscalar processor which includes a floating point unit with forced arithmetic results, microcode to handle special cases, pipeline bypass, and early result generation can be avoided because architectural approaches for handling out-of-order results allow dependencies to be resolved irrespective of result reordering. Therefore, the early and out-of-order generation of forced results may be handled by a reorder buffer.

Title
Floating point processing unit with forced arithmetic results
Application Number
8/533812
Publication Number
5748516
Application Date
September 26, 1995
Publication Date
May 5, 1998
Inventor
Kelvin D Goveas
Austin
TX, US
Michael D Goddard
Austin
TX, US
Agent
Skjerven Morrill MacPherson Franklin & Friel L
Agent
David W O Brien
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 7/00
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