05742822 is referenced by 80 patents and cites 6 patents.

A multithreaded processor includes an instruction pipelined unit 140 and a register file 120 composed of a plurality of register banks 130. The register file 120 is coupled to an external memory 190 through register frame load/store lines 121, so that a register frame, which is defined as a content stored in one register bank 130, can be loaded and stored in bundle. When a thread parallel start instruction and a thread sequential start instruction are executed, the register frames are saved through the load/store lines 121. When a thread end instruction and a thread return instruction are executed, the register frames are restored through the load/store lines 121.

Title
Multithreaded processor which dynamically discriminates a parallel execution and a sequential execution of threads
Application Number
8/575145
Publication Number
5742822
Application Date
December 19, 1995
Publication Date
April 21, 1998
Inventor
Masato Motomura
Tokyo
JP
Agent
Foley & Lardner
Assignee
NEC Corporation
JP
IPC
G06F 9/40
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