05729152 is referenced by 35 patents and cites 107 patents.

A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The memory device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. The memory device includes a resynchronization circuit which allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation. Thus, each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations. In one embodiment, multiple memory devices are coupled to a common, high-speed I/O bus without requiring large bus drivers and complex bus receivers in the memory modules.

Title
Termination circuits for reduced swing signal lines and methods for operating same
Application Number
270856
Publication Number
5729152
Application Date
October 27, 1995
Publication Date
March 17, 1998
Inventor
Fu Chieh Hsu
Saratoga
CA, US
Winston Lee
South San Francisco
CA, US
Wingyu Leung
Cupertino
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Agent
E Eric Hoffman
Norman R Klivans
Assignee
Monolithic System Technology
CA, US
IPC
H03K 17/16
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