05721935 is referenced by 76 patents and cites 10 patents.

A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.

Title
Apparatus and method for entering low power mode in a computer system
Application Number
580027
Publication Number
5721935
Application Date
February 18, 1997
Publication Date
February 24, 1998
Inventor
John E Larson
Katy
TX, US
Michael J Collins
Tomball
TX, US
James R Edwards
Longmont
CO, US
James R Reif
Houston
TX, US
Todd J DeSchepper
Houston
TX, US
Agent
Pravel Hewitt Kimball & Krieger
Assignee
Compaq Computer Corporation
TX, US
IPC
G06F 1/32
View Original Source