05712815 is referenced by 206 patents and cites 3 patents.

An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and a reference cell array (22) having a plurality of reference core cells which are selected together with a selected memory core cell. A precharge circuit (36a) is used to precharge all of the array bit lines and the reference bit lines to a predetermined potential prior to a program operation. A reference generator circuit (134) is used for selectively generating one of a plurality of target memory core cell bit line program-verify voltages, each one corresponding to one of a plurality of programmable memory states. A switching circuit (P1,N1) is used to selectively connect a program current source to the selected certain ones of the columns of array bit lines containing the selected memory core cells which are to be programmed. A sensing logic circuit (26,27) continuously compares a potential on one of the selected bit lines and one of the plurality of target program-verify voltages. The sensing logic circuit generates a logic signal which is switched to a low logic level when the potential on the selected bit line falls below the selected one of the plurality of target program-verify voltages. The switching circuit is responsive to the low logic level for disconnecting the program current source so as to inhibit further programming of the selected memory core cells.

Title
Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells
Application Number
8/635995
Publication Number
5712815
Application Date
April 22, 1996
Publication Date
January 27, 1998
Inventor
Sameer S Haddad
San Jose
CA, US
Colin S Bill
Cupertino
CA, US
Agent
Davis Chin
Assignee
Advanced Micro Devices
CA, US
IPC
G11C 16/06
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