According to one aspect of the invention, a semiconductor memory has, as word lines, a layer of high-resistance signal lines that are paralleled in a separate layer by low-resistance signal lines. Each high-resistance signal line is divided into segments separated by gaps. Interconnections between the high- and low-resistance signal lines in each word line are aligned with the gaps in the high-resistance signal lines in the adjacent word lines. According to a second aspect of the invention, the low-resistance signal lines extend, from alternate directions, to approximately the midpoints of the high-resistance signal lines. The high-resistance signal lines are undivided, or are divided into only two segments apiece. The high- and low-resistance signal lines are interconnected at the midpoints, or at the midpoints and one end.