05705409 is referenced by 86 patents and cites 17 patents.

A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Title
Method for forming trench transistor structure
Application Number
8/535397
Publication Number
5705409
Application Date
September 28, 1995
Publication Date
January 6, 1998
Inventor
Keith E Witek
Austin
TX, US
Agent
Keith E Witek
Assignee
Motorola
IL, US
IPC
H01L 21/265
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