05696927 is referenced by 114 patents and cites 8 patents.

A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression component may further include a decompression fault handler and a compression fault handler, each executable on the execution unit.

Title
Memory paging system and method including compressed page mapping hierarchy
Application Number
8/576100
Publication Number
5696927
Application Date
December 21, 1995
Publication Date
December 9, 1997
Inventor
Steve Cox
Austin
TX, US
Drew Dutton
Austin
TX, US
James R MacDonald
Buda
TX, US
Agent
Skjerven Morrill MacPherson Franklin & Friel L
Agent
David W O Brien
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 12/08
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