05694556 is referenced by 50 patents and cites 46 patents.

A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. Each bus to bus bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a minor image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the bus to bus bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions.

Title
Data processing system including buffering mechanism for inbound and outbound reads and posted writes
Application Number
8/472603
Publication Number
5694556
Application Date
June 7, 1995
Publication Date
December 2, 1997
Inventor
Steven M Thurber
Austin
TX, US
Edward J Silha
Austin
TX, US
Dan M Neal
Round Rock
TX, US
Agent
Anthony V S England
Raymond M Jenkens & Gilchrist Galasso
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 13/14
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