05689517 is referenced by 66 patents and cites 6 patents.

The present invention discloses an apparatus for controlling and observing test data stored in scannable-D-flip-flops independent of a system clock, thereby making the scannable-D-flip-flops well suited for partial scanning Design-For-Test (DFT) techniques. Under the present invention, the scannable-D-flip-flop is comprised of two master latches and one slave latch such that the scannable-D-flip-flops may operate in a normal mode of operation or a scan/test mode of operation. During normal mode of operation, the first master latch operates together with the slave latch in response to the system clock. During the scan/test mode of operation, the second master latch operates together with the slave latch in response to a scan clock. Since the scanning of external test data is controlled by the scan clock, the conventional non-scannable D-flip-flops in the design, which are controlled by the system clock, maintain their previous states during a scanning operation. Also disclosed is a method for performance testing integrated circuits utilizing the scanning application of the scannable-D-flip-flops. This is accomplished by constructing a test circuit that spans the entire silicon die area. By using a special AC-TEST-MODE control signal, the scannable D-flip-flops are set to a "flow-through" mode to provide a direct path through the scannable flip-flops such that the test circuit forms an oscillator in which the frequency of the device can be measured.

Apparatus for scannable D-flip-flop which scans test data independent of the system clock
Application Number
Publication Number
Application Date
July 26, 1996
Publication Date
November 18, 1997
Kamalesh Ruparel
San Jose
Blakely Sokoloff Taylor & Zafman
Apple Computer
G01R 31/28
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