05684977 is referenced by 39 patents and cites 24 patents.

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect. The transaction execution circuitry pipelines memory access requests from the data processors, and includes invalidation circuitry for processing each writeback request from a given data processor prior to activation to determine if the Dtag index corresponding to the victimized cache line is invalid. Thereafter, the invalidation circuitry activates writeback requests only if the Dtag index is not invalid and cancels the writeback request if the Dtag index is invalid.

Title
Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
Application Number
8/415040
Publication Number
5684977
Application Date
March 31, 1995
Publication Date
November 4, 1997
Inventor
Louis F Coffin III
San Jose
CA, US
Paul Loewenstein
Palo Alto
CA, US
Kevin Normoyle
San Jose
CA, US
Satyanarayana Nishtala
Cupertino
CA, US
Zahir Ebrahim
Mountain View
CA, US
William C Van Loo
Palo Alto
CA, US
Agent
Gary S Flehr Hohbach Test Albritton & Herbert Williams
Assignee
Sun Microsystems
CA, US
IPC
G06F 12/08
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