05680575 is referenced by 5 patents and cites 13 patents.

A system for resetting a cache in a first device connected by a multilinelink to a memory in a second device. A transceiver in the first element connects to one end of each of the link lines and a transceiver in the second device connects to the other end. The transmitter in the first device transceiver is disabled in response to a failure of the transceiver to receive messages from the second device. The transmitter in the first device transceiver also selectively sends a reset sequence to the receiver in the second device. A detector detects when all of the receivers in the second device have either received a reset sequence or have detected that a transmitter in the first device is disabled. The detector sets a latch in response, representing that data in the second device cache is invalid. Optionally, the second device has responders which send responses over the link lines indicating receipt of a reset sequence. The transmitters in the first device switch to a disabled state when the responses are not received within a specified period.

Title
Interconnect failure detection and cache reset apparatus
Application Number
839657
Publication Number
5680575
Application Date
May 17, 1995
Publication Date
October 21, 1997
Inventor
Douglas Wayne Westcott
Rhinebeck
NY, US
Gregory Salyer
Woodstock
NY, US
Thomas Anthony Gregg
Highland
NY, US
Louis Thomas Fasano
Poughkeepsie
NY, US
Robert Stanley Capowski
Verbank
NY, US
Neil George Bartow
Saugerties
NY, US
Agent
Whitham Curtis Whitham & McGinn
Agent
Lynn L Augspurger
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 13/14
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