05659952 is referenced by 263 patents and cites 28 patents.

A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.

Title
Method of fabricating compliant interface for semiconductor chip
Application Number
309433
Publication Number
5659952
Application Date
December 29, 1994
Publication Date
August 26, 1997
Inventor
John W Smith
Palo Alto
CA, US
Thomas H Distefano
Monte Sereno
CA, US
Craig Mitchell
Santa Clara
CA, US
Zlata Kovac
Los Gatos
CA, US
Agent
Lerner David Littenberg Krumholz & Mentlik
Assignee
Tessera
CA, US
IPC
H05K 3/34
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