05659710 is referenced by 78 patents and cites 8 patents.

A cache coherency method and system are provided for ensuring coherency of accessed data for each bus master of a plurality of bus masters in a processing system, wherein at least some bus masters have a cache means connected to a system bus, which provides communication to a main memory for access of data stored therein. Each of these at least some bus masters also includes snoop monitor logic, e.g., residing within a bus interface unit (BIU), for monitoring the presence of a coherent memory transaction on the system bus and for broadcasting in response thereto a unidirectional snoop response signal with reference to the bus master's caching means whenever the coherent memory transaction is initiated by other than that bus master. The snoop monitors are electrically interconnected, with each snoop monitor receiving at a separate signal input the unidirectional snoop response signal broadcast by each other snoop monitor of the plurality of snoop monitors. Each snoop response signal broadcast comprises one snoop response of a set of N predetermined snoop responses, each snoop response being M binary bits in length with a single bit of each snoop response being broadcast in a single clock cycle of the processing system such that M binary bits are preferably transferred over M consecutive clock cycles, wherein M.gtoreq.1 and N=2.sup.M.

Cache coherency method and system employing serially encoded snoop responses
Application Number
Publication Number
Application Date
November 29, 1995
Publication Date
August 19, 1997
John Edward Derrick
Kevin Lee Sherman
Essex Junction
Heslin Rothenberg P C
International Business Machines Corporation
G06F 13/16
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