05658806 is referenced by 98 patents and cites 3 patents.

A method for fabricating a self-aligned thin-film transistor, in accordance with the present invention, first involves forming a gate electrode on an insulating layer. Next, a gate dielectric layer is formed to enclose the gate electrode. Subsequently, a semiconductor layer, a conducting layer, and a first dielectric layer are formed to cover the substrate and the gate dielectric layer. Afterwards, a chemical mechanical polishing process is applied to subsequently polish the first dielectric layer and the conducting layer to expose the semiconductor layer above the gate electrode. Therefore, the conducting layer disposed at opposite sides of the gate electrode is self-aligned to act as the source/drain regions of the fabricated TFT device.

Title
Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
Application Number
8/547715
Publication Number
5658806
Application Date
October 26, 1995
Publication Date
August 19, 1997
Inventor
Chun Yen Chang
Hsinchu
TW
Hsiao Yi Lin
Hualien Hsien
TW
Liang Po Chen
Hsinchu
TW
Horng Chih Lin
Hsinchu
TW
Agent
Fish & Richardson P C
Assignee
National Science Council
TW
IPC
H01L 21/465
H01L 21/265
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