05652859 is referenced by 47 patents and cites 21 patents.

A method and apparatus for snooping both cache memory and associated buffer queues in a cache subsystem arrangement. Since there are usually several requests for cache data being handled at any given time under high performance operation of multiple processors, a cache arrangement includes at least one buffer queue for storing the address of the cache data line and the status of the cache data line, which facilitate keeping track of the data requests and handling them efficiently. In response to a snoop request, a snoop address is compared to the address stored in the buffer queue so as to provide a positive comparison result if the snoop address matches the address stored in the buffer queue, thereby indicating a snoop hit condition. The buffer queue of the cache arrangement further has a snoop hit bit for storing a record of the positive comparison result that indicates the snoop hit condition. Even if there is still a pending transaction involving the buffer queue, the snoop request of the cache is satisfied once the comparison result has been stored in the snoop hit bit of the buffer queue, thereby keeping the cache high performance for local code while at the same time providing efficient support for snoop requests.

Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues
Application Number
Publication Number
Application Date
August 17, 1995
Publication Date
July 29, 1997
Sorin Iacobovici
San Jose
Dean Mulla
San Jose
Jack A Lenell
Institute for the Development of Emerging Architectures L L C
G06F 12/00
View Original Source