05651125 is referenced by 236 patents and cites 39 patents.

A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.

Title
High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations
Application Number
146382
Publication Number
5651125
Application Date
July 10, 1995
Publication Date
July 22, 1997
Inventor
William M Johnson
Austin
TX, US
David B Witt
Austin
TX, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 15/167
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