05648283 is referenced by 84 patents and cites 21 patents.

A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444). Trench (80) defines vertically-oriented source and body layers (86, 90) stacked along oxide layer (460) to form vertical channels on opposite sides of trench (80). Layers (86, 90) have a lateral thickness (88) of the undercut sidewalls (444) and rims (447) spacers. Conductor (94) contacts the N-source and P-body layers, and enhanced P+ region in trench (80).

Title
High density power device fabrication process using undercut oxide sidewalls
Application Number
927169
Publication Number
5648283
Application Date
January 31, 1994
Publication Date
July 15, 1997
Inventor
John W Mosier II deceased
late of Bend
OR, US
Theodore O Meyer
Austin
TX, US
Douglas A Pike Jr
Bend
OR, US
Dumitru Sdrulla
Bend
OR, US
Dah Wen Tsang
Bend
OR, US
Agent
Marger Johnson McCollom & Stolowitz P C
Assignee
Advanced Power Technology
OR, US
IPC
H01L 49/00
H01L 21/265
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