05646545 is referenced by 343 patents and cites 5 patents.

A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiment, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof. The PLD switches between configurations sequentially, by random access, or on command from an external or internal signal. This reconfiguration allows the PLD to function in one of N configurations, wherein N is equal to the maximum number of memory cells assigned to each programmable point. In this manner, a PLD with a number M of actual CLBs functions as if it includes M times N effective CLBs.

Title
Time multiplexed programmable logic device
Application Number
8/516186
Publication Number
5646545
Application Date
August 18, 1995
Publication Date
July 8, 1997
Inventor
Jennifer Wong
Fremont
CA, US
Robert Anders Johnson
San Jose
CA, US
Richard A Carberry
Los Gatos
CA, US
Stephen M Trimberger
San Jose
CA, US
Agent
Norman R Klivans
Jeanette S Harms
Assignee
Xilinx
CA, US
IPC
H03K 19/173
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