05640048 is referenced by 135 patents and cites 16 patents.

A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package. Fabricated from two pieces of symmetrical printed circuit board material, this embodiment reduces ground bounce for IC current sourcing as well as IC current sinking, and provides approximately a 100% improvement in thermal dissipation as compared to prior art BGA packages.

Title
Ball grid array package for a integrated circuit
Application Number
273331
Publication Number
5640048
Application Date
September 20, 1996
Publication Date
June 17, 1997
Inventor
Erich Selna
Mountain View
CA, US
Agent
Flehr Hohbach Test Albritton & Herbert
Assignee
Sun MicroSystems
CA, US
IPC
H01L 29/40
H01L 23/52
H01L 23/48
View Original Source