Integrated circuit I/O using a high performance bus interface United States Patent 05638334

05638334 is referenced by 158 patents and cites 69 patents.

The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.

Title
Integrated circuit I/O using a high performance bus interface
Application Number
510898
Publication Number
5638334
Application Date
May 24, 1995
Publication Date
June 10, 1997
Inventor
Mark Horowitz
Palo Alto
CA, US
Michael Farmwald
Berkeley
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Rambus
CA, US
IPC
G11C 8/00
View Original Source

Citations: 158 (view full list)

  1. Terry R Lee, Joseph M Jeddeloh: Reconfigurable memory module and method. Micron Technology, Dorsey & Whitney, October 10, 2006: US07120727 (163 worldwide citation)
  2. Joseph M Jeddeloh: Memory hub with internal cache and/or memory access prediction. Micron Technology, Dorsey & Whitney, November 7, 2006: US07133972 (105 worldwide citation)
  3. Joseph M Jeddeloh: System and method for on-board diagnostics of memory modules. Micron Technology, Dorsey & Whitney, April 24, 2007: US07210059 (100 worldwide citation)
  4. Ely Tsern: Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology. Rambus, Vierra Magen Marcus & DeNiro, December 9, 2008: US07464225 (97 worldwide citation)
  5. Joseph M Jeddeloh, Terry Lee: System and method for selective memory module power management. Micron Technology, Dorsey & Whitney, September 23, 2008: US07428644 (85 worldwide citation)
  6. Joseph M Jeddeloh, Terry Lee: System and method for selective memory module power management. Micron Technology, Dorsey & Whitney, October 14, 2008: US07437579 (72 worldwide citation)
  7. Mark W Kellogg, Timothy J Dell, Erik L Hedberg, Claude L Bertin: Programmable burst length DRAM. International Business Machines Corporation, Robert A Walsh, Whitham Curtis Whitham, April 20, 1999: US05896404 (62 worldwide citation)
  8. Richard M Barth, Ely K Tsern, Craig E Hampel, Frederick A Ware, Todd W Bystrom, Bradley A May, Paul G Davis: System for a memory device having a power down mode and method. Rambus, Vierra Magen Marcus & DeNiro, August 25, 2009: US07581121 (61 worldwide citation)
  9. James W Meyer, Cory Kanski: Arbitration system and method for memory responses in a hub-based memory system. Micron Technology, Dorsey & Whitney, October 10, 2006: US07120743 (60 worldwide citation)
  10. Paul A LaBerge: Delay line synchronizer apparatus and method. Micron Technology, Dorsey & Whitney, December 27, 2005: US06980042 (59 worldwide citation)

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