05638334 is referenced by 158 patents and cites 69 patents.

The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.

Title
Integrated circuit I/O using a high performance bus interface
Application Number
510898
Publication Number
5638334
Application Date
May 24, 1995
Publication Date
June 10, 1997
Inventor
Mark Horowitz
Palo Alto
CA, US
Michael Farmwald
Berkeley
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Rambus
CA, US
IPC
G11C 8/00
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